This invention relates to digital memory circuits, and in particular to dynamic random access memory (DRAM)circuits. The invention teaches a circuit and a method for extending the row activation time of one or multiple banks of DRAM, thereby increasing the number of bits per second that may be written or read from the DRAM.
Nearly all DRAM architectures include arrays of memory cells. FIG. 1 shows a portion of a typical DRAM circuit with a row of memory cells 110a-n. A row may, for example, contain 1024 memory cells, and there may be many rows within an array (not shown). Each cell typically has capacitor 102a for storing charge, and pass transistor 104a that passes the charge on capacitor 102a to data, or bit, line 106a. Sense amplifier 108a on bit line 106a detects and holds (latches) the logic state of the memory cell when the cell is activated.
Typically, a row of memory cells are simultaneously activated by a wordline 120. The wordline turns on the gate of the pass transistor, and allows charge to flow to or from the storage capacitor. This allows the data stored in the cell to be read by the sense amplifier (i.e. latch the sense amplifier), or new data, as latched into the sense amplifier, may be written to the cell.
Selecting a new row with a wordline takes a relatively long time. First, the new row's address must be decoded by partial row decoder 160, before the wordline is activated by row activation circuit 130. Second, wordlines have capacitance and series resistance, which results in an RC time constant that increases the time it takes for the wordline to reach its full active voltage. Third, charging all the cells on a wordline may result in voltage transients that are equal in magnitude to the signal output of the storage capacitor. These transients must settle before the memory cell contents may be reliably read. Therefore, the access time between selecting a wordline and fetching that data from the sense amplifiers is relatively long (about 30 ns).
Additionally, adjacent rows of memory cells typically share sense amplifiers, so one row may need to be deactivated, that is, have its wordline turned off, before another row is activated. Deactivation requires a restore and precharge cycle to set the memory cell to its desired logic state. The restore cycle removes the voltage on the currently active wordline. The precharge cycle engages the precharge circuit 105a so that the bitlines are equilibrated in preparation for the next row activation. These operations can take an additional 20 ns. Thus, it typically takes about 50 ns to precharge and close an active row, and then about 30 ns to open a new row and read its contents.
Information from an active row (one having an active wordline, that is, a wordline with a voltage above an activation voltage) may be read/written faster than from an inactive row because the sense amplifiers are already latched to the state they have read from the storage capacitors. Data may be read from the sense amplifiers in about 10 ns as long as that row is open. No precharging, restoring, or row access operations need to be performed. Likewise, write operations to currently active rows can be done in a fraction of the time that it takes to perform a precharge operation and activate a new row. If a row can be held open longer, or if more rows could be held open, the performance of the DRAM would improve by allowing more bits/second to pass in and out of the memory.
However, there are inherent limitations imposed on how long a row can be kept active. If pass transistor 104a is NMOS, its gate (the wordline 120) must be boosted above the source voltage (V.sub.DD) by at least the threshold voltage (V.sub.T) of pass transistor 104a to achieve an activation voltage sufficient to write or restore the storage capacitor 102a to a full V.sub.DD level. Therefore, the wordline 120 shown in FIG. 1, when activated, is generally boosted above V.sub.DD as disclosed by McAlexander, et al. in U.S. Pat. No. 4,533,843, Aug. 6, 1985. Such boosting is typically done by creating a boosted voltage in boot-strap generator (boost generator) 150. The boosted voltage is commonly referred to as phi.sub.-- bs and is also commonly referred to as "boot-strapped."
Each boost operation transfers a finite amount of charge from the boost generator circuit to a boosted node, and the voltage at the boosted node decays over time as this charge leaks off the node. Because of this boosted voltage loss, DRAMs are typically specified with a maximum row activation time. That is, the time the wordline stays above V.sub.DD +V.sub.T after the wordline has been boosted.
To extend this activation time, circuit designers have devised ways to pump active boosted nodes with additional charge. Some methods use either free running or clocked auxiliary pump circuits (not shown). These auxiliary pump circuits add incremental charge to phi.sub.-- bs on a repeating pump cycle, keeping phi.sub.-- bs at a relatively constant voltage.
These techniques share at least two problems. The first problem is that auxiliary pump circuits take up relatively large amounts of chip area. This increases the chip size for a given memory array site.
The second problem is that for the wordline to reach full phi.sub.-- bs, the gate voltage of wordline driver transistor 132 must be greater than phi.sub.-- bs plus the threshold voltage of this transistor. This requires that the gate node of the driver transistor (n2) 135 be double-boosted to a double-boosted voltage (not shown). This double-boosted node loses charge, and hence drops in voltage, similarly to the wordline. Thus, the row activation time is also limited by the decay time of the gate voltage on driver transistor 132. Auxiliary pump circuits do not restore this node to a double-boosted voltage, and therefore these methods have limited row activation times.
Maintaining all boosted nodes in the row and sense path at boosted and double-boosted voltage levels for an indefinite period of time promises a significant increase in the data bandwidth of memory chips. It is furthermore desirable that this be accomplished without additional pump circuitry, without interrupting read and write operations, and without complex, bandwidth-limiting control logic.